module zl_2346_pre2(clr,clk,set,datain,en,codeout);
	input [15:0] datain; //输入16位二进制数
	input clr, set, clk; //clr 清零 clk 时钟信号 set 置数	
	output reg[2:0] en; //位选(0~3)
	output reg[7:0] codeout; //7段译码器输出
	
	reg[3:0] data; //由二进制拆分开的十六进制数	
	reg [15:0] B; //显示的16位二进制数
	reg[15:0] time_count;//时间计数
	
   //录数
	always@(posedge clk)
	begin
		if(clr) B <= 16'd0; //高电平清零
		else if(set) B <= datain;		
	end
	

	//计时，clk控制交换速度
	always@ (posedge clk)
		begin
			time_count = time_count + 1;
			if(time_count == 400)
				time_count <= 16'b0;
		end
	
	//位选显示
	always@ (posedge clk)
    begin
		  if(time_count >= 300 && B[15:12] != 0)
            begin
               en <= 4'b011;
               data <= B[15:12];
            end
        else if(time_count >= 200 && !(B[15:12] == 0 && B[11:8] == 0))
            begin
                en <= 4'b010;
                data <= B[11:8];
            end
        else if(time_count >= 100 && !(B[15:12] == 0 && B[11:8] == 0 && B[7:4] == 0))
            begin
                en <= 4'b001;
                data <= B[7:4];
            end	
        else if(time_count >= 0)
            begin
                en <= 4'b000;
                data <= B[3:0];
            end
    end
	 
	//7段译码器输出
	always@ (data)
	begin
		case(data)
			4'h0:codeout<=8'h3f;
			4'h1:codeout<=8'h06;
			4'h2:codeout<=8'h5b;
			4'h3:codeout<=8'h4f;
			4'h4:codeout<=8'h66;
			4'h5:codeout<=8'h6d;
			4'h6:codeout<=8'h7d;
			4'h7:codeout<=8'h07;
			4'h8:codeout<=8'h7f;
			4'h9:codeout<=8'h6f;
			4'ha:codeout<=8'h77;
			4'hb:codeout<=8'h7c;
			4'hc:codeout<=8'h39;
			4'hd:codeout<=8'h5e;
			4'he:codeout<=8'h79;
			4'hf:codeout<=8'h71;
			default: codeout<=8'h00;
		endcase
	end
			
endmodule 